An open language for communicating Printed Circuits Specifications, Requirements and Capabilities
Aliases: “Stack up”, “stackups”, “buildup”, “build up”
We generally use “layers” as a way of describing stackups in CircuitData. You’ll find that in addition to the usual parts of a stackup (dielectrics and conductive layers), there are several more functions that are defined as layers here. If you have a “free stackup”, meaning that the manufacturer is free to choose the materials the have in stock as long as they comply with the demands specified, or you want to set a specific stackup that are not to deviate from. You can use the options set under the “configuration” and “stackup” object. In here, you will be able to set if the stackup is locked and thus cannot be changed. You can also specify if the order of the layers (both inner and outer) is ordered properly. Unordered layers will often be the consequence of exports from systems that don’t have a total overview of all the layers, so please pay attention to this.
Aliases:
You describe both rigid and flexible conductive layers under the layers section of a product. Each layer must be represented by one item, so a four layer board should have four items under layers with the function being “conductive”. You also need to describe the material, e.g. copper. A conductive layer can have a lot of attributes, so make sure that you read the documentation.
Aliases: “Surface finish”, “finish”, “surfacefinish”, “finalfinish”
You describe one or more final finishes under the layers section of a product. Each final finish must be represented by one item with the function being “final_finish”. You also need to describe the material, e.g. ENIG. A layer of final finish can have a lot of attributes, so make sure that you read the documentation.
Aliases: “laminates”, “dielectricum”
Dielectrics are defined as layers. It is very important that you also define a material and refer to that in the layers. Make sure that you read the documentation.
Aliases: “solder mask”, “solder resist”
Soldermasks are defined as layers. It is very important that you also define a material and refer to that in the layers. Make sure that you read the documentation. To just define a top or bottom soldermask, or e.g. two on top, make sure that you place the order number of the layer inn accordance with the conductive layers.
Aliases: “silk screen”, “silkscreen”
Legends are defined as layers. Make sure that you read the documentation. To just define a top or bottom legend, make sure that you place the order number of the layer inn accordance with the conductive layers. The color of the legend and the thickness is set on the layer and its attributes.
Aliases:
Stiffeners are defined as layers. Make sure that you read the documentation. Make sure that you place the order number of the layer inn accordance with the conductive layers to get the correct placement.
Aliases:
Coverlays are defined exactly like a Soldermask but with the “flexible” tag set to “true”.
Aliases:
Peelable masks are defined as layers. Make sure that you read the documentation. Make sure that you place the order number of the layer inn accordance with the conductive layers to get the correct placement.
Aliases: “kapton”, “kapton tape”
Peelable masks are defined as layers. Make sure that you read the documentation. Make sure that you place the order number of the layer inn accordance with the conductive layers to get the correct placement.
Aliases:
Conductive carbon print is defined as a conductive layer with a material set to “carbon”.
Aliases:
Silver print is defined as a conductive layer with a material set to “silver”.
Aliases:
All requirements for the inner packaging of the finished products can be defined in the “logistical” object under the “inner_packaging” object.
Aliases: “PCB”
The size and thickness of the board/PCB is set under the “metrics” object in the “board” object.
Aliases: “array”, “panel”, “circuit board”
All attributes and processes of/on the array/custom panel is set under the “metrics” object in the “array” object.
Aliases:
Defined as a process with the function set to “depth_routing”.
Aliases:
Defined as a process with the function set to “counterboring”.
Aliases:
Defined as a process with the function set to “countersink”.
Aliases:
Defined as a process with the function set to “punching”.
Aliases:
Defined as a process with the function set to “plated_edges”.
Aliases:
Defined as a process with the function set to “plated_slots”.
Aliases:
Defined as a process with the function set to “hole” and “castellated” set to true.
Aliases:
Defined as a process with the function set to “coin_attachment”.
Aliases:
Defined as a layer with the function set to “hard_gold” and a placement attribute of “selective_pads”
Aliases:
Defined as a layer with the function set to “hard_gold” and a placement attribute of “edge_connectors”
Aliases: “lot-code”, “lot number”, “datecode”, “serial number”
Placed in the “configuration” part, this describes the markings needed. Generally you will find LOT/Batch codes here and also serial numbers. Markings are tied up to layers by the name of the layer.
Aliases:
Placed in the “configuration” part, this describes the standards that the finished product needs to be comply with. Check out this for potential standards. Please note that if you want to have Halogen Free material, you can add “iec_61249-2-21” to the required standard
Aliases: “via protection”
Type I: “Tended single or double sided”. Soldermask material is dryfilm. Hole “filled” must be with “soldermask”. Type II: “Tended and covered single or double sided”. Soldermask material is dryfilm. Hole “filled” must be with “soldermask”. Hole “covered” is true Type III: “Plugged single or double sided”. Hole “filled” must with be with “soldermask”. Type IV: “Plugged and covered single or double sided”. Hole “filled” must with be with “soldermask”. Hole “covered” is true Type V: “Filled (fully plugged)”. Hole “filled” must with be with “soldermask”. Type VI: “Filled and covered single or double sided”. Hole “filled” must with be with “resin”. Hole “covered” is true Type VII: “Filled and capped”. Hole “filled” must with be with “resin”. Hole “covered” is true. Hole “capped” is true.